International Conference on Computer and Knowledge Engineering

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Area-Efficient VLSI Implementation of Bit-Serial Multiplier Using Polynomial Basis over GF(2m)

Authors :

Saeideh Nabipour¹ Javad Javidan² Gholamreza Zare Fatin³

1- University of Mohaghegh Ardabili 2- University of Mohaghegh Ardabili 3- University of Mohaghegh Ardabili

Keywords :

Area-efficient architecture،irreducible polynomial،bit serial multiplier،normal basis multiplier،GF(2m) multiplier

Abstract :

A finite field multiplier is a fundamental operation that can be widely applied in many areas such as error correction codes and signal processing. For these specific applications, the arithmetic unit that demands the highest amount of resources is the multiplier. This operation is particularly challenging as it necessitates a significant allocation of logical components. In this paper, a novel enhanced technique for multiplying serial in parallel out method and an interleaved approach for modular reduction are investigated. The proposed methodology presents an area efficient structure in contrast to alternative algorithms put forth in the existing scholarly work. The finite field multiplier's complexity is reduced in a specific architecture by utilizing the logic NAND gate. The effectiveness of the suggested framework is assessed by employing complexity metrics pertaining to time aspects such as latency and critical path, as well as hardware aspects such as the number of gate-latches. The suggested multiplier decreases area complexity for m = 163 by 17.46% when compared to one of the most area-efficient multipliers currently available. The multiplier that has been suggested demonstrates superior performance compared to the two most similar multipliers when considering both area and latency. This conclusion is based on an FPGA design that evaluated the three multipliers.

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