International Conference on Computer and Knowledge Engineering

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Implementation of a Low-Overhead 2-Bit Parity-Preserving Reversible Vedic Multiplier for Quantum Architectures

Authors :

Shekoofeh Moghimi¹ Negin Mashayekhi² Mohammad Reza Reshadinezhad³

1- university of isfahan 2- university of isfahan 3- university of isfahan

Keywords :

Quantum Computing،Reversible Logic،Parity Preserving،Fault-Tolerant،Quantum Vedic Multiplier

Abstract :

Reversible logic, by enabling computations without loss of information, offers a promising approach to significantly reduce energy dissipation, making it a key technology for low-power and quantum computing systems. Parity-preserving reversible circuits further enhance reliability enabling fault detection in nanoscale systems. Multiplication, a fundamental operation in computing and signal processing, benefits significantly from efficient reversible designs. However, existing reversible Vedic multipliers often suffer from excessive Quantum Cost (QC), Garbage Outputs (GO), and Constant Inputs (CI). This paper proposes two new 2-bit parity-preserving reversible quantum Vedic multipliers, serving as the foundational block for scalable n-bit multipliers, that is enhanced to reduce quantum metrics without compromising performance. The proposed circuits are simulated using Quirk tool to test their correct functionality. Comparative analysis shows that the best proposed design outperforms existing architectures on average by 34%, 53%, and 9% in constant inputs, garbage outputs, and quantum cost, respectively, providing a fault-tolerant, cost-efficient, and scalable solution for next-generation quantum computing systems.