International Conference on Computer and Knowledge Engineering

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Improving Soft Error Reliability of FPGA-based Deep Neural Networks with Reduced Approximate TMR

Authors :

Anahita Hosseinkhani¹ Behnam Ghavami²

1- Shahid Bahonar University of Kerman 2- Shahid Bahonar University of Kerman

Keywords :

Deep Neural Network, FPGA, SEU, Hardening, Reliability

Abstract :

Deep Neural Networks (DNN) are used in many types of applications such as autonomous driving, detecting cancer, and also space exploration. Indeed, these applications require a certain level of reliability. More recently, FPGA devices have become a target platform for DNN applications due to their high flexibility and computational power. Unfortunately, the SRAM-based FPGAs are considered to be susceptible to soft errors which can lead to errors in execution. Triple Modular Redundancy (TMR) is one of the effective mitigation techniques for masking SEUs for FPGA but causes an increase in power consumption and area overhead. In this paper, we evaluate the reliability of MNIST DNN implemented in Xilinx SRAM-based FPGA. Through fault injection simulation, we identified the most vulnerable parts of the design that SEU can generate errors. We improve the SEU reliability of DNN with our proposed hardening strategy named Reduced Approximate Triple Modular Redundancy. SEU reliability was improved by selectively applying reduced approximate TMR to the most critical layers of MNIST DNN, achieving a 40% improvement in reliability with increasing 8% resources and 4% power consumption.