International Conference on Computer and Knowledge Engineering

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MIPS-Core Application Specific Instruction-Set Processor for IDEA Cryptography − Comparison between Single-Cycle and Multi-Cycle Architectures

Authors :

Ahmad Ahmadi¹ Reza Faghih Mirzaee²

1- Dept. of Computer Engineering, West Tehran Branch, Islamic Azad University, Tehran, Iran 2- Dept. of Computer Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran, Iran

Keywords :

ASIP،Single-Cycle Processor،Crypto Processor،Cryptography،International Data Encryption Algorithm

Abstract :

A single-cycle processor completes the execution of an instruction in only one clock cycle, albeit with a relatively long clock period. In contrast, although clock frequency is higher in a multi-cycle processor, it takes several clock cycles to finish an instruction. A crucial question, serving educational objectives as well, pertains to the performance of each solution. This paper presents a new Instruction-Set Architecture (ISA) for International Data Encryption Algorithm (IDEA) cryptography. The new design is an Application Specific Instruction-set Processor (ASIP) that supports both general-purpose and specific instructions. It is a single-cycle MIPS-core architecture with an average Clock per Instruction (CPI) of 1. Also, a comparative analysis is presented in this paper, highlighting the differences between the new processor and a comparable multi-cycle crypto processor. The FPGA implementation results show that both architectures have almost the same encoding/decoding throughput. However, the previous processor consumes nearly twice as many resources as the new one.

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